Intel hits major High-NA EUV milestone, explores larger photomasks to cut costs
Intel has processed over one million 300-mm wafers using High-NA EUV scanners, a first for the industry, with its fleet now including three ASML tools. The company is currently using standard 6-inch photomasks that require stitching for large chips, but it is developing 6×12-inch photomasks to enable full-field exposure without stitching. This achievement reflects both increased tool count and process maturity, with Intel using these systems for its 18A node and Panther Lake processors.
Intel's cumulative wafer count jumped from roughly thirty thousand in early 2025 to over one million by late 2026, a surge driven by adding a third scanner and the faster EXE:5200B model. This total includes wafers from installation, certification, research, and actual manufacturing, with the tools now producing Panther Lake chips on the 18A node.
The company currently relies on standard masks that expose only half-fields, forcing large dies to be stitched together. This method cuts throughput significantly and demands precise alignment to avoid defects. Intel is therefore developing larger 6x12-inch masks to enable single-exposure full fields, which would eliminate stitching-related design and yield complications.
Intel's progress with High-NA EUV could accelerate the production of complex, high-performance chips, potentially lowering costs for advanced processors and AI accelerators. If larger photomasks succeed, manufacturers may see fewer defects and higher throughput, which could translate into more affordable consumer electronics. However, the industry's reliance on Intel's early adoption may create a competitive imbalance, as rivals could face higher barriers to entry. Ultimately, this milestone may influence global supply chains and the pace of technological advancement.